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8 - channel, 12 - bit, configurable adc/dac with on - chip reference, i 2 c interface data sheet ad5593r rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology w ay, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com features 8 - channel, configurable adc/dac/gpio configurable as any combination of 8 12 - bit dac channels 8 12 - bit adc channels 8 general - purpose i/o pins integrated temperature sensor 16 - lead tssop package i 2 c interface applications control and monitoring general - purpose analog and digital i/o general description the ad5593r has eight input/output (i/o) pins, which can be in dependently configured as digital - to - analog converter (dac) outputs, analog - to - digital converter (adc) inputs, digital outputs, or digital inputs. when an i/o pin is configured as an analog output, it is driven by a 12 - bit dac. the output range of the dac is 0 v to v ref or 0 v to 2 v ref . when an i/o pin is configured as an analog input, it is connected to a 12 - bit adc via an analog multiplexer. the input range of the adc is 0 v to v ref or 0 v to 2 v ref . the i/o pins can also be configured to be general - purpose, digital input or output (gpio) pins. the state of the gpio pins can be set or read back by accessing the gpio write data register and gpio read configuration registers, respectively, via an i 2 c write or read operation. the ad5593r has an integrated 2.5 v, 20 ppm/c reference that is turned off by default and an integrated temperature indicator that gives an indication of the die temperature. the temperature value is read back as part of an adc read sequence. the ad5593r is available in a 16 - lead tssop and operates over a temperature range of ?40c to +105c. table 1 . related products product description ad5592r ad5593r equivalent with spi interface ad5592r -1 ad5593r equivalent with spi interface and v logic pin functional block dia gram figure 1. reset v ref i/o7 i/o0 gpio7 gpio0 t/h sequencer v dd v logic gnd scl sda a0 temperature indicator dac register input register dac 7 dac register input register dac 0 ad 5593 r mux 12-bit successive approximation adc power-on reset i 2 c interface logic 2.5v reference 12507-001
ad5593r data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ..................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing charact eristics ................................................................ 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 14 theory of operation ...................................................................... 16 dac section ................................................................................ 16 adc section ............................................................................... 16 gpio section .............................................................................. 17 internal reference ...................................................................... 17 reset function ............................................................................ 17 temperature indicator ............................................................... 17 serial interface ................................................................................ 18 write operation .......................................................................... 18 read operation ........................................................................... 18 pointer byte ................................................................................. 20 control registers ........................................................................ 20 general - purpose control register .......................................... 21 configuring the ad5593r ........................................................ 22 dac write operation ................................................................ 23 dac read back ............................................................................ 23 adc operation .......................................................................... 24 gpio operation ......................................................................... 25 three - state pins .......................................................................... 25 85 k? pull - down pins ............................................................... 25 power - do wn/reference control .............................................. 26 reset function ............................................................................ 26 applications information .............................................................. 27 microprocessor interfacing ....................................................... 27 ad 5593r to adsp - bf537 interface ....................................... 27 layout guidelines ....................................................................... 27 outline dimensions ....................................................................... 28 ordering guide ............................................................................... 28 revision history 8 /14 revision 0 : initial version
data sheet ad5593r rev. 0 | page 3 of 28 specifications v dd = 2.7 v to 5.5 v, v ref = 2.5 v (internal), t a = t min to t max , unless otherwise noted. table 2 . parameter min typ max unit test conditions/comments adc performance f in = 10 khz sine wave resolution 12 bits input range 1 0 v ref v adc range select bit = 0 0 2 v ref v adc range select bit = 1 integral nonlinearity (inl) ?2 +2 lsb differential nonlinearity (dnl) ?1 +1 lsb offset error 5 mv gain error 0.3 % fsr track time (t track ) 2 500 ns conversion time (t conv ) 2 2 s signal to noise ratio (snr) 3 69 db v dd = 2.7 v, input range = 0 v to v ref 67 db v dd = 5.5 v, input range = 0 v to v ref 61 db v dd = 5.5 v, input range = 0 v to 2 v ref signal - to - noise + distortion (sinad) ratio 69 db v dd = 2.7 v, input range = 0 v to v ref 67 db v dd = 3.3 v, input range = 0 v to v ref 60 db v dd = 5.5 v, input range = 0 v to 2 v ref total harmonic distortion (thd) ?91 db v dd = 2.7 v, input range = 0 v to v ref ?89 db v dd = 3.3 v, input range = 0 v to v ref ?72 db v dd = 5.5 v, input range = 0 v to 2 v ref spurious free dynamic range (sfdr) 91 db v dd = 2.7 v, input range = 0 v to v ref 91 db v dd = 3.3 v, input range = 0 v to v ref 72 db v dd = 5.5 v, input range = 0 v to 2 v ref aperture delay 2 15 ns v dd = 3 v 12 ns v dd = 5 v aperture jitter 2 50 ps channel - to - channel isolation ?95 db f in = 5 khz full power bandwidth 8.2 mhz at 3 db 1.6 mhz at 0.1 db dac performance 4 resolution 12 bits output range 0 v ref v dac range select bit = 0 0 2 v ref v dac range select bit = 1 inl ?1 +1 lsb dnl ?1 +1 lsb offset error ?3 +3 mv offset error drift 2 8 v/c gain error 2 0.1 % fsr zero code error 0.65 2 mv total unadjusted error (tue) 0.03 0.25 % fsr output range = 0 v to v ref 0.015 0.1 % fsr output range = 0 v to 2 v ref capacitive load stability 2 nf r load = 10 nf r load = 1 k? resistive load 1 k ? short - circuit current 25 ma dc crosstalk 2 ?4 +4 v s ingle channel, full - scale output change dc output impedance 0.2 ? dc power supply rejection ratio (psrr) 2 0.15 mv/v dac code = midscale, v dd = 3 v 10% or 5 v 10% load impedance at rails 5 25 ?
ad5593r data sheet rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments load regulation 200 v/ma v dd = 5 v 10%, dac code = midscale, ?10 ma i out + 10 ma 200 v/ma v dd = 3 v 10%, dac code = midscale, ?10 ma i out + 10 ma power - up time 7 s exiting power - down mode, v dd = 5 v ac specifications slew rate 1.25 v/s settling time 6 s dac glitch impulse 2 nv - sec dac to dac crosstalk 1 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 1 nv - sec digital feedthrough 0.1 nv - sec multiplying bandwidth 240 khz dac code = full scale, output range = 0 v to 2 v ref output voltage noise spectral density 200 nv/ hz dac code = midscale, output range = 0 v to 2 v ref , measured at 10 khz snr 81 db sfdr 77 db sinad 74 db total harmonic distortion ?76 db reference input v ref input voltage 1 v dd v dc leakage current ?1 +1 a no i/o x pins configured as dacs v ref input impedance 12 k ? dac output range = 0 v to 2 v ref 24 k ? dac output range = 0 v to v ref reference output v ref output voltage 2.495 2.5 2.505 v v ref temperature coefficient 20 ppm/ c capacitive load stability 5 f r l oad = 2 k ? output impedance 0.15 ? v dd = 2.7 v 0.7 ? v dd = 5 v output voltage noise 10 v p - p 0.1 hz to 10 hz density 240 nv/hz at ambient, f = 1 khz, c l = 10 nf line regulation 2 0 v/v at ambient, sweeping v dd from 2.7 v to 5.5 v 1 0 v/v at ambient, sweeping v dd from 2.7 v to 3.3 v load regulation sourcing 210 v/ma at ambient, ?5 ma load current + 5 ma sinking 120 v/ma at ambient, ?5 ma load current + 5 ma output current load capability 5 ma v dd 3 v gpio output i source and i sink 1.6 ma output voltage high , v oh v dd ? 0.2 v i source = 1 ma low, v ol 0.4 v i source = 1 ma gpio input input voltage high , v ih v dd 0.7 v low , v il v dd 0.3 v input capacitance 20 pf hysteresis 0. 2 v input current 1 a
data sheet ad5593r rev. 0 | page 5 of 28 parameter min typ max unit test conditions/comments logic inputs input voltage high , v inh 0.7 v logic v low, v inl 0.3 v logic v input current, i in ?1 +0.01 +1 a input capacitance, c in 10 pf logic output (sda) output high voltage, v oh v logic ? 0.2 v i source = 200 a; v dd = 2.7 v to 5. 5 v output low voltage, v ol 0.4 v i sink = 200 a floating - state output capacitance 10 pf temperature sensor 2 resolution 12 bits operating range ?40 +105 c accuracy 3 c track time 5 s adc buffer enabled 20 s adc buffer disabled power requirements v dd 2.7 5.5 v i dd 2.7 digital inputs = 0 v or v dd power - down mode 3.5 a normal mode v dd = 5 v 1.6 ma i/o0 to i/o7 are dacs, internal reference, gain = 2 1 ma i/o0 to i/o7 are dacs, external reference, gain = 2 2.4 ma i/o0 to i/o7 are dacs and sampled by the adc, internal reference, gain = 2 1.1 ma i/o0 to i/o7 are dacs and sampled by the adc, external reference, gain = 2 1 ma i/o0 to i/o7 are adcs, internal reference, gain = 2 0.75 ma i/o0 to i/o7 are adcs, external reference, gain = 2 0.5 ma i/o0 to i/o7 are general - purpose outputs 0.5 ma i/o0 to i/o7 are general - purpose inputs v dd = 3 v 1.1 ma i/o0 to i/o7 are dacs, internal reference, gain = 1 1 ma i/o0 to i/o7 are dacs, external reference, gain = 1 1.1 ma i/o0 to i/o7 are dacs and sampled by the adc, internal reference, gain = 1 0.78 ma i/o0 to i/o7 are dacs and sampled by the adc, external reference, gain = 1 0.75 ma i/o0 to i/o7 are adcs, internal reference, gain = 1 0.5 ma i/o0 to i/o7 are adcs, external reference, gain = 1 0.45 ma i/o0 to i/o7 are general - purpose outputs 0.45 ma i/o0 to i/o7 are general - purpose inputs 1 when using the internal adc buffer, there is a dead band of 0 v to 5 mv. 2 guaranteed by design and characterization ; not production tested. 3 all specifications expressed in decibels are referred to full - scale input, fsr, and tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 dc specifications tested with the outputs unloaded, unless otherwise noted. linearity calculated using a reduced code range of 8 to 408 5. an u pper dead band of 10 mv exists when v ref = v dd . 5 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 ? typical channel res istance o f the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 ? 1 ma = 25 mv ( see figure 24 and figure 25).
ad5593r data sheet rev. 0 | page 6 of 28 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2 ; v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd ; 2.5 v v ref v dd ; a ll specifications t min to t max , unless otherwise noted. table 3 . parameter 1 min typ max unit conditions/comments t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd,sta , start/repeated start condition hold time t 5 100 ns t su, dat , data setup time t 6 2 0.9 s t hd, dat , data hold time t 7 0.6 s t su,sta , setup time for repeated start t 8 0.6 s t su,sto , stop condition setup time t 9 1.3 s t buf , bus free time between a stop and a start condition t 10 300 ns t r , rise time of scl and sda when receiving 0 ns t r , rise time of scl and sda when receiving (cmos compatible) t 11 250 ns t f , fall time of sda when transmitting 0 ns t f , fall time of sda when receiving (cmos compatible) 300 ns t f , fall time of scl and sda when receiving 20 + 0.1c b 3 ns t f , fall time of scl and sda when transmitting c b 3 400 pf capacitive load for each bus line 1 guaranteed by design and characterization; not production tested. 2 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min o f the scl signal) to bridge the undefined region of the falling edge of scl . 3 c b is the total capacitance of one bus line in pf. t r and t f are measured between 0.3 v dd and 0.7 v dd . figure 2. 2 - wire serial interface timing diagram start condition repeated start condition stop condition sda scl t 9 t 3 t 10 t 4 t 6 t 5 t 2 t 11 t 7 t 4 t 1 t 8 12507-002
data sheet ad5593r rev. 0 | page 7 of 28 absolute maximum rat ings t a = 25c , unless otherwise noted. transient currents of up to 100 ma do not cause scr latch - up. table 4 . paramet er rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v logic + 0.3 v digital output voltage to gnd ?0.3 v to v logic +0.3 v v ref to gnd ?0.3 v to v dd +0.3 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) +150c lead temperature jedec industry - standard soldering j - std -020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond th e maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja unit 16 - lead tssop 112 c/w esd caution
ad5593r data sheet rev. 0 | page 8 of 28 pin configuration an d function descripti ons figure 3. 16 - lead tssop pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 reset asynchronous reset pin. tie this pin high for normal operation. when this pin is brought low, the ad5593r is reset to its default configuration. 2 a0 address input. sets the lsb of the 7 - bit slave address. 3 v dd power supply input. the ad5593r can operate from 2.7 v to 5.5 v. decouple the supply with a 0.1 f capacitor to gnd. 4 to 7, 10 to 13 i/o0 to i/o7 input/output 0 through input/output 7. these pins can be independently configured as dacs, adcs, or general - purpose digital inputs or outputs. the function of each pin is determined by programming the appropriate bits in the configuration registers. 8 v ref reference input/output. when the internal reference is enabled , the 2.5 v reference voltage is available on the pin. a 0.1 f capacitor connected from the v ref pin to gnd is recommended to achieve the specified performance from the ad5593r . when the internal reference is disabled, an external reference must be applied to this pin. the voltage range for the external reference is 1 v to v dd . 9 v logic interface power supply. the v oltage ranges from 1.8 v to 5.5 v. 14 gnd groun d reference point for all circuitry. 15 sda serial data input. this pin is used in conjunction with the scl line to clock data into or out of the input shift register. sda is a bidirectional, open - drain line that must be pulled to the v logic supply with a n external pull - up resistor. 16 scl serial clock line. this is used in conjunction with the sda line to clock data into or out of the 16 - bit input register. 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 11 1 0 9 a0 v dd i/o0 i/o3 i/o2 i/o1 reset sda gnd i/o7 i/o4 v ref v logic i/o5 i/o6 scl ad5593r top view (not to scale) 12507-003
data sheet ad5593r rev. 0 | page 9 of 28 typical performance characteristics figure 4. adc inl; v dd = 5.5 v figure 5. adc dnl; v dd = 5.5 v figure 6. adc inl; v dd = 2.7 v figure 7. adc dnl; v dd = 2.7 v figure 8 . histogram of adc codes; v dd = 2.7 v figure 9. histogram of codes; v dd = 5.5 v inl (lsb) adc code ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1000 2000 3000 4000 12507-102 dnl (lsb) adc code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 1000 2000 3000 4000 12507-103 inl (lsb) adc code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 1000 2000 3000 4000 12507-104 dnl (lsb) adc code ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 1000 2000 3000 4000 12507-105 number of occurrences adc code 0 5000 10000 15000 20000 25000 30000 35000 2528 2529 2530 v dd = 2.7v samples = 60000 v in = 1.5v gain = 1 external reference = 2.5v 12507-100 number of occurrences adc code 0 5000 10000 15000 20000 25000 30000 35000 v dd = 5.5v samples = 60000 v in = 1.5v gain = 1 external reference = 2.5v 2520 2521 2522 2523 2524 2525 2526 12507-101
ad5593r data sheet rev. 0 | page 10 of 28 figure 10 . adc bandwidth figure 11 . dac inl figure 12 . dac dnl figure 13 . dac adjacent code glitch figure 14 . dac digital to analog glitch (rising) figure 15 . dac digital to analog glitch (falling) adc bandwidth (db) frequency (hz) 1k 10k 100k 1m 10m 100m ?6 ?5 ?4 ?3 ?2 ?1 0 1 v dd = 3v/5v 12507-124 inl (lsb) dac code ?1.0 ?0.5 0 0.5 1.0 0 1024 2048 3072 4095 12507-130 dnl (lsb) dac code ?1.0 ?0.5 0 0.5 1.0 0 1024 2048 3072 4095 12507-127 glitch (nv-sec) dac code ?4 ?2 0 2 4 0 1024 2048 3072 4095 12507-126 v out (v) time (s) ?10 0 10 20 2.490 2.495 2.500 2.505 2.510 12507- 1 15 v out (v) time (s) ?10 0 10 20 2.490 2.495 2.500 2.505 2.510 12507- 1 16
data sheet ad5593r rev. 0 | page 11 of 28 figure 16 . dac settling time (100 code change, rising edge ) figure 17 . dac settling time (100 code change, falling edge) figure 18 . dac settling time, output r ange = 0 v to v ref figure 19 . dac settling time, output r ange = 0 v to 2 v ref figure 20 . dac settling time vs. capacitive load figure 21 . dac 1/f noise with external reference v out (v) time (s) ?10 ?5 0 5 10 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 12507- 1 19 v out (v) time (s) ?10 ?5 0 5 10 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 12507-120 v out (v) time (s) 0.50 2.00 1.75 1.50 1.25 1.00 0.75 0 1 2 3 4 5 r l = 2k c l = 200pf 12507-131 v out (v) time (s) 1.0 4.0 3.5 3.0 2.5 2.0 1.5 0 1 2 3 4 5 r l = 2k c l = 200pf 12507-132 v out (v) time (s) ?5 0 5 10 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0nf load 10nf load 22nf load 47nf load 12507-121 v out (v p-p) time (seconds) ?200 ?150 ?100 ?50 0 50 100 150 200 0 4 8 2 6 10 12507-109
ad5593r data sheet rev. 0 | page 12 of 28 figure 22 . dac 1/f noise with internal reference figure 23 . dac output noise spectral density figure 24 . dac output sink and so urce capability, output range = 0 v to v ref figure 25 . dac output sink and source capability, output range = 0 v to 2 v ref v out (v p-p) time (seconds) ?200 ?150 ?100 ?50 0 50 100 150 200 0 4 8 2 6 10 12507- 1 10 nsd (nv/hz) frequency (hz) 0 500 1000 1500 2000 2500 10 1k 100k 100 10k 1m full-scale 3/4 scale mid-scale 1/4 scale zero scale 12507- 1 12 output voltage (v) load current (ma) 0 5 4 3 2 1 ?30 ?20 ?10 0 10 20 30 full-scale 3/4 scale 1/2 scale 1/4 scale zero scale 12507-133 output voltage (v) load current (ma) ?1 0 6 5 4 3 2 1 ?30 ?20 ?10 0 10 20 30 full-scale 3/4 scale 1/2 scale 1/4 scale zero scale 12507-134
data sheet ad5593r rev. 0 | page 13 of 28 figure 26 . internal reference 1/f noise figure 27 . reference n oise s pectral d ensity figure 28 . reference l ine r egulation v out (v p-p) time (seconds) ?20 ?15 ?10 ?5 0 5 10 15 20 0 4 8 2 6 10 12507- 11 1 nsd (nv/hz) frequency (hz) 0 200 400 600 800 1000 1200 10 1k 100k 100 10k 1m 12507- 1 13 v ref (v) v dd (v) 12507-200 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 2.4995 2.4997 2.4999 2.5001 2.5003 2.5005
ad5593r data sheet rev. 0 | page 14 of 28 terminology adc integral nonlinearity (inl) for the adc, inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end points of the tr ansfer function are zero scale, a point that is 1 lsb below the first cod e transition, and full scale, a poin t that is 1 lsb above the last code transition. adc differential nonlinearity (dnl) for the adc, dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error offset error is the deviation of the first code transition (00 000) to (00 001) from the ideal, that is, agnd + 1 lsb. gain error gain error is the deviation of the last code transition (111 110) to (111 111) from the ideal (that is, v ref ? 1 lsb) after the offset error has been a djusted out. channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full - scale 5 khz sine wave signal to all nonselected adc input channels and determining how much th at signal is attenuated in the selected channel. this specification is the worst case across all adc channels for the ad5593r . adc power supply rejection ratio (psrr) for the adc, variations in power supply affect the full - scale transition, but not the converter linearity. power supply rejection i s the maximum change in the full - scale transition point due to a change in power supply voltage from the nominal value. track - and - hold acquisition time the track - and - hold amplifier goes into track mode when the adc sequence register has been written to. the track and hold amplifier goes into hold mode when the conversion starts (see figure 34 ). track - and - hold acquisition time is the minimum time required for the track - and - hold amplifier to remain in track mode for its output to reach and settle to within 1 lsb of the applied input signal, given a step change to the input signal. signal -to - (noise + distortion) ratio (sinad) sinad is the measured ratio of signal to (noise + distortion) at the output of the analog - to - digital converter. the signal is the rms amplitude of the fundamental. noise is th e sum of all non - fundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical sinad for an ideal n- bit converter with a sine wave input is given by signal- to - (noise + distortion) (db) = 6.02 n + 1.76 thus for a 12 - bit converter, this is 74 db. adc total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for th e ad5593r , it is defined as ( ) 1 65432 v vvvvv thd 22222 log20db ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. p eak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. dac relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonline arity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 11 . dac differential nonlinearity (dnl) for the dac, differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maxi mum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 12 . zero code error zero code error is a measurement of the output error when zero code (0x000) is loaded to the dac register. ideally, the output is 0 v. the zero code error is always positive in the ad5593r because the output of the dac c annot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero code error is expressed in mv. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer charact eristic from the ideal expressed as % of fsr. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error can be negative or positive. offset e rror drift offset error drift is a measurement of the change in offset error with a change in temperature. it is expressed in v/c.
data sheet ad5593r rev. 0 | page 15 of 28 dac dc power supply rejection ratio (psrr) for the dac, psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v. v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time output voltage settling time is the amo unt of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change and is measured from the rising edge of sda that generates the stop condition. digital -to - analog glitch impulse digital - to - analog glitch impuls e is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - sec, and is measured when the digital input code is changed by 1 lsb at the major ca rry transit ion (0x7ff to 0x800) (see figure 14 and figure 15). digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - sec, and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vic e versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density (nsd) nsd is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density is shown in figure 23. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - sca le output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another d ac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of an other dac. it is measured in standalone mode and is expressed in nv - sec. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is first measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then it is measured by execut ing a software ldac and monitor ing the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - sec. dac -t o - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa), using the write to and update command s while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv - sec. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this finite bandwidth . a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. dac total harmonic distortion (thd) for the dac, thd is th e difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. voltage reference temperatu re coefficient (tc) voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the voltage reference tc is calculated using the box method, which defines the tc as the maximum change in the reference outpu t over a given tempera ture range expressed in ppm/c , as follows; 6 ) ( ) ( ) ( 10 ? ? ? ? ? ? ? ? ? = range temp v v v tc nom ref min ref max ref where: v ref (max) is the maximum reference output measured over the total temperature range. v ref (min) is the minimum reference output measured over the total temperature range. v ref (nom) is the nominal reference output voltage, 2.5 v. te mp range is the specified temperature range of ?40c to +105c.
ad5593r data sheet rev. 0 | page 16 of 28 theory of operation the ad5593r is an 8 - channel, configurable analog and digital i/o port. the ad5593r has eight pins that can be independently configured as a 12 - bit dac output channel, a 12 - bit adc input channel, a digital input pin, or a digital output pin. the function of each pin is determined by programming the adc, dac, or gpio configura tion registe rs as appropriate. dac section the ad5593r contains eight 12 - bit dacs. each dac consists of a string of resistors followed by an output buffer amplifier. figure 29 shows a block diagram of the dac architecture. figure 29 . dac channel architecture block diagram the dac channels share a single dac range bit (see bit d4 in table 11) that sets the output range to 0 v to v ref or 0 v to 2 v ref . because the range bit is shared by all channels, it is not possible to set different output ranges on a per channel basis. the input coding to the dac is straight binary. therefore, the ideal output voltage is given by ? ? ? ? ? ? = n ref out d v g v 2 where: g = 1 for an output range of 0 v to v ref or g = 2 for an output range of 0 v to 2 v ref . v ref is the voltage on the v ref pin. d is the decimal equivalent of the binary code (0 to 4095) that is loaded to the dac register. n = 12. resistor string the simplified segmented resistor string dac structure is shown in figure 30. the code loaded to the dac register determines the switch on the string that is connected to the output buffer. because each resistance in the string has the same value, r, the string dac is guaranteed monotonic. figure 30 . resistor string dac output buffer the output buffer is designed as an input/output rail - to - rail buffer. the output buffer can drive 2 nf capacitance with a 1 k? resistor in parallel. the slew rate is 1.25 v/s with a ? to ? scale settling time of 6 s. by default, the dac outputs update di rectly after data has been written to the inp ut register. the ldac register delay s the updates until additional channels have been written to if required. see the ldac mode operation section for more information. adc section the adc section is a fast, 12 - bit, single - supply adc with a conversion time of 2 s. the adc is preceded by a multiplexer that switches selected i/o pins to the adc. a sequencer is included to swit ch the multiplexer to the next selected channel automatically. channels are selected for conversion by writing to the adc sequence register. when the write to the adc sequence register has completed, the first channel in th e conversion sequence is put in to track mode. each channel can track the input signal for a minimum of 700 ns. the conversion is initiated on the rising edge of the clock for the acknowledge ( ack ) that occurs after the slave address (see figure 34). each conversion takes 2 s. the adc has a range bit (adc range select in the general - purpose control register, see bit d5 in table 11 ) that sets the input range as 0 v to v ref or 0 v to 2 v ref . all input channels share the same range. the output coding of the adc is straight binary. it is possible to set each i/o x pin as both a dac and an adc. in this case, the primary function is that of the dac. if the pin is selected for inclusion in an adc conversion sequence, the voltage on the pin is converted and made available via the serial interface. this allows the dac voltage t o be monitored. dac register ref (+) v ref i/ox gnd ref () resistor string output amplifier 12507-0 1 1 to output amplifier r r r r r 12507-012
data sheet ad5593r rev. 0 | page 17 of 28 gpio section each of the eight i/o x pins can be configured as a general - purpose digital input or output pin by programming the gpio control register. when an i/o x pin is configured as an output, the pin can be set high or low by programmin g the gpio write data register. logic levels for general - purpose outputs are relative to v dd and gnd. when an i/o x pin is configured as an input, its status can be determined by reading the gpio read configuration register. when an i/o x pin is set as an ou tput, it is possible to read its status by also setting it as an input pin. when reading the status of the i/o x pins set as inputs the status of an i/o x pin set as both and input and output pin is also returned. internal reference the ad5593r contains an on - chip 2.5 v reference. the reference is powered down by default and is enabled by setting bit d9 in the power - down/reference control register to 1. when the on - chip reference is powered up, the reference voltage appears on the v ref pin and may be used as a reference source for other components. when the internal reference is used, it is recommended to decouple v ref to gnd using a 100 nf capacitor . it is recommended that the internal reference be buffered before using it elsewhere in the system. when the reference is powered down , an external reference must be connected to v ref . suitable external reference sources for the ad5593r includ e the ad780 , ad1582 , adr431 , ref193 , and adr391 . reset function the ad5593r has an asynchronous reset pin. for normal o peration, reset is tied high. a falling edge on reset resets all registers to their default values and reconfigures the i/o pins to their default values (85 k? pull - down resistor to gnd). the reset function tak es 250 s maximum; do not write new data to the ad5593r during this time. the ad5593r has a software reset that performs the same function as the reset pin. the reset function is activated by writing 0x0f to the pointer byte and 0x05 and 0xac to the most significant and least significant bytes, respectively. temperat ure indicator the ad5593r contains an integrated temperature indicator that can be read to provide an estimation of the die temperature. this can be used in fault detection where a sudden rise i n die temperature may indicate a fault condition , such as a shorted output. temperature readback is enabled by setting bit d8 in the adc sequence register. the temperature result is then added to the adc sequence. the temperature result has an address of 0 b1000 and care must be taken that this result is not confused with the readback from dac0. the temperature conversion takes 5 s with the adc buffer enabled and 20 s when the buffer is disabled. calculate t he temperature using the following formula: 654 . 2 82 ? 25 c) ( code adc e temperatur + = the range of codes returned by the adc when reading from the temperature indicator is approximately 645 to 1035, corresponding to a temperature between ?40c to +105c. the accuracy of the temperature indicator is typically 3c.
ad5593r data sheet rev. 0 | page 18 of 28 serial interface the ad5593r has a 2 - wire, i 2 c - compatible serial interface (refer to the i 2 c - bus specification , version 2.1, january 2000). the ad5593r is connected to an i 2 c bus as a slave device under the control of a master device. see figure 2 for a timing diagram of a typical write sequence. the ad5593r supports standard mode (100 khz) and fast mode (400 khz). support i s not provided for 10 - bit addressing and general call addressing. the ad5593r has a 7 - bit slave address ; its six msbs are set to 00 1000. the lsb is set by the state of the a0 address pin, which determines the state of the a0 bit. the facility to change the logic level of the a0 pin before a read or write operation allows the user to incorporate multiple ad5593r devices on one bus. the 2 - wire serial bus protocol operates as follows: the master initiates data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bi t slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device wai ts for data to be written to or read from its shift register. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of s cl and remain stable during the high period of scl. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition. in read mode, t he master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. write operation when writing to the ad5593r , the user must begin with a start command followed by an address byte r/ w = 0), after which the ad5593r acknowledges that it is prepared to receive data by pulling sda low. the ad5593r requires three bytes of data. the first byte is the pointer byte. this byte contains information def ining the type of operation that is required of the ad5593r , such as configuring the i/o pins and writing to a dac. the pointer byte is followed by the m ost s ignificant b yte and the l east s ignificant b yte, as shown in figure 31 . after these data bytes are acknowledged by the ad5593r , a stop c ondition follows. read operation when reading data back from the ad5593r , the user begins with a start comma nd followed by an address byte ( r/ w = 0), after which the dac ackno wledges that it is prepared to transmit data by pulling sda low. the pointer byte is then written to select what is to be read back. a repeat start or a new i 2 c transmission can then follow to read two bytes of data from the ad5593r . both bytes are acknowledged by the master, as shown in figure 32. it is also possible to perform consecutive readbacks without having to provide interim start and stop conditions or slave addresses. this method can be used to read blocks of conversions from the adc, as shown in figure 34. figure 31 . 4 - byte i 2 c write frame 2 pointer byte frame 1 slave address 1 9 9 1 scl start by master ack. by ad5593r ack. by ad5593r ack. by ad5593r ack. by ad5593r sda r/w d7 a0 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 1 9 9 1 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 12507-013
data sheet ad5593r rev. 0 | page 19 of 28 figure 32 . read one 16 - bit word figure 33 . read one 16 - bit word, maintain control of the bus frame 2 pointer byte frame 1 slave address frame 2 most significant data byte frame 3 least significant data byte frame 1 slave address start by master ack. by ad5593r ack. by ad5593r start by master ack. by ad5593r ack. by master stop by master stop by master nack. by master 1 9 9 1 scl sda w d7 a0 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 1 9 scl (continued) sda (continued) scl (continued) sda (continued) d7 d6 d5 d4 d3 d2 d1 d0 1 9 9 1 r d15 a0 0 0 1 0 0 0 d14 d13 d12 d11 d10 d9 d8 12507-014 start by master repeat start by master ack. by ad5593r ack. by master stop by master nack. by master ack. by ad5593r ack. by ad5593r scl (continued) sda (continued) scl (continued) sda (continued) frame 2 pointer byte frame 1 slave address 1 9 9 1 scl sda w d7 a0 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 1 9 frame 3 least significant data byte d7 d6 d5 d4 d3 d2 d1 d0 frame 2 most significant data byte frame 1 slave address 1 9 9 1 r d15 a0 0 0 1 0 0 0 d14 d13 d12 d11 d10 d9 d8 12507-015
ad5593r data sheet rev. 0 | page 20 of 28 figure 34 . i 2 c block read pointer byte the pointer byte contains eight bits. bits[d7:d4] are mode bits that select the operation to be executed . the data contained in bits[d3:d0] depend on the operation require d. table 7 shows the configuration of the pointer byte. when bits[d7:d4] are 0b0000, the mode dependent bits (bits [d3:d0] ) select a control register to write data to. the data written to a control register is contained in the msb and lsb as shown in figure 31 . the mode dependent data bits also select which dac i s updated during a dac write operation and which register is selected for readback. table 7 . pointer byte configu ration d7 d6 d5 d4 d3 d2 d1 d0 mode bits mode dependent data bits table 8 . mode bits d7 d6 d5 d4 description 0 0 0 0 configuration mode 0 0 0 1 dac write 0 1 0 0 adc readback 0 1 0 1 dac readback 0 1 1 0 gpio readback 0 1 1 1 register readback control registers table 9 shows the control register map for the ad5593r . the control registers c onfigure the i/o pins and set various operating parameters in the ad5593r , such as enabling the reference, selecting the ldac mode function, or selecting power - down modes. the control registers are written to using the 4 - byte i 2 c write sequence shown in figure 31 . to write to a control register , the mode bits (bits [d7:d4]) of the pointer byte are zeros. the m ode dependent data bits (bits[d3:d0]) of the pointer byte select which control register is to be accessed. the data to be written to the control register is contained in the most significant and least significant data bytes. th ese contain a total of 16 bit s and are shown as d15 to d0 in table 10 and table 11 . the contents of the co ntrol registers can be read back using the read sequence shown in figure 32 or figure 33 . start by master ack. by ad5593r ack. by ad5593r scl (continued) sda (continued) scl (continued) sda (continued) scl (continued) sda (continued) frame 2 pointer byte frame 1 slave address 1 9 9 1 scl sda w d7 a0 0 0 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 1 9 frame 3 least significant data byte d7 d6 d5 d4 d3 d2 d1 d0 1 9 d15 d14 d13 d12 d11 d10 d9 d8 frame 4 most significant data byte frame 2 most significant data byte frame 1 slave address 1 9 9 1 repeat start by master ack. by ad5593r ack. by master ack. by master ack. by master r d15 a0 0 0 1 0 0 0 d14 d13 d12 d11 d10 d9 d8 1 9 ack. by master frame 5 least significant data byte stop by master d7 d6 d5 d4 d3 d2 d1 d0 1 only applicable if an adc sequence has been selected. start of adc conversion 1 12507-016
data sheet ad5593r rev. 0 | page 21 of 28 general - purpose control regi ster the general - purpose control register enables or disables certain functions associated with the dac, adc , and i/o pin configura - tion (see table 11 ). the register set s the output range of the dac and input range of the adc, which sets their transfer functions, enable s /disable s the adc buffer, and enables the precharge function (see the adc section for more details). the register is also used to lock the i/o pin configuration to prevent accidental change. when bit d7 is set to 1, writes to the configuration registers are ignored. table 9 . control registers pointer byte [d7:d0] register n ame description default value 00000000 nop no operation 0x0000 00000010 adc sequence register selects adcs for conversion 0x0000 00000011 general - purpose control register dac and adc control register 0x0000 00000100 adc pin configuration selects which pins are adc inputs 0x0000 00000101 dac pin configuration selects which pins are dac outputs 0x0000 00000110 pull - down configuration selects which pins have a n 85 k ? pull - down resistor to gnd 0x00ff 00000111 ldac mode selects the operation of the load dac 0x0000 00001000 gpio write configuration selects which pins are general - purpose outputs 0x0000 00001001 gpio write data write s data to general - purpose outputs 0x0000 00001010 gpio read configuration selects which pins are general - purpose inputs 0x0000 00001011 power - down/reference control power s down the dacs and enable s /disable s the reference 0x0000 00001100 open - drain configuration select s open - drain or push - pull for general - purpose outputs 0x0000 00001101 three - state pins selects which pins are three - stated 0x0000 00001110 reserved 00001111 software reset resets the ad5593r 0x0000 table 10 . general - purpose control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved adc buffer precharge adc buffer enable lock configuration write all dacs adc range select dac range select reserved table 11 . general - purpose control register descriptions bits description d15 to d10 reserved. set these bits to 0. d9 adc buffer precharge. 0: the adc buffer is not used to precharge the adc. if the adc buffer is enabled, it is always powered up (default) . 1: the adc buffer is used to precharge the adc. if the adc buffer is enabled, it is powered up while the conversion takes place and then powered down until the next conversion takes place. d8 adc buffer enable. 0: the adc buffer is disabled (default). 1: the adc buffer is enabled. d7 lock configuration . 0: the contents of the i/o pin configuration registers can be changed (default). 1: the contents of the i/o pin configuration registers cannot be changed. d6 write all dacs. 0: for future dac writes, the dac address bits determine which dac is written to (default). 1: for future dac writes, the dac address bits are ignored and all channels configured as dacs are updated with the same data . d5 adc range select. 0: the adc range is 0 to v ref (default). 1: the adc range is 0 to 2 v ref . d4 dac range select. 0: the dac range is 0 to v ref (default). 1: the dac range is 0 to 2 v ref . d3 to d0 reserved; set these bits to 0.
ad5593r data sheet rev. 0 | page 22 of 28 configuring the ad5593r the ad5593r i/o pins are configured by writing to a series of pin configuration registers. the control registers are accessed when bits[d7:d4] are 0b0000. bits[d3:d0] determine which register is accessed as shown in table 9 . on power - up, the i/o pins are configured as 85 k? resistors connected to gnd. the i/o channels of the ad5593r can be configured to operate as dac outputs, adc inputs, digital outputs, digital inputs, three - state, or connected to gnd with 85 k? pull - down resistors. when configured as digital outputs, the pins have the additional option of being configured as push/pull or open - drain. the i/o channels are configured by writing to the appropriate configuration registers, as shown in table 9 . t o assign a particular function for an i/o channel, write to the appropriate register and set the corresponding bit to 1. for example, setting bit d0 in the dac configuration register configures i/o0 as a dac. in the event that the bit for an i/o channel is set in multiple configuration reg isters, the i/o channel adopts the function dictated by the last write operation. the exceptions to this rule are that an i/o x pin can be set as both a dac and adc or as a digital input and output. when an i/o x pin is configured as a dac and adc, the prim ary function is as a dac and the adc can be used to measure the voltage being provided by the dac. this feature can be used to monitor the output voltage to detect short circuits or overload conditions. figure 35 s hows an example of how to configure i/o1 and i/o7 as dacs. when a pin is configured as both a general - purpose input and output, the primary function is as an output pin. this configuration all ows the status of the output pin to be determined by reading the gpio read configuration register. the general - purpose control register contains a lock configuration bit. when the lock configuration bit is set to 1, any writes to the pin configuration reg isters are ignored, thus preventing the function of the i/o pins from being changed. the i/o pins can be reconfigured any time when the ad5593r is in an idle state, that is, no adc conversions are taking place and no registers are being read back. the lock configuration bit must also be set to 0. table 12. i/o pin configuration registers 1 d7 d6 d5 d4 d3 d2 d1 d0 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 setting an i/o pin configuration bit to 1 after writing to a control register enables that function on the selected i/o pin. figure 35 . configuring i/o1 and i/o7 as dacs s = start condition p = stop condition a = acknowledge a p s a a 0b00000101 0b00000000 0b10000010 a pointer byte most significant data byte least significant data byte slave address + w 12507-017
data sheet ad5593r rev. 0 | page 23 of 28 dac write operation data is written to a dac when the mode bits (bits[d7:d4]) of the pointer byte are 0b0001 ( see table 8 ) . bits[d2:d0] determine which dac is addressed. data to be written to the dac is contained in the msb and lsb, as shown in table 15. data is written to the selected dac input register. data written to the input register can be automatically copied to the dac register , if required. data is transferred to the dac register b ased on the setting of the ldac mode register (see table 13 ). ldac mode operation the transfer of data from an input register to a dac register is controlled by bit d 1 and bit d0 of the r eadback and ldac mode register (pointer byte = 0b00000111). when the ldac mode bits (bit d1 and bit d0) are set to 00 , new data is automatically transferred from the input register to the dac register and the analog output updates. whe n the ldac mode bits are set to 01, data remains in the input register. this allows writes to input registers without affecting the analog outputs. after loading the input registers with the desired values and setting the ldac mode bits to 10 , the values i n the input registers transfer to the dac registers and the analog outputs update simultaneously. the l dac mode bits then revert to 01. table 13 . ldac mode register d1 d0 ldac mode 0 0 data written to an input register is immediately copied to a dac register and the dac output updates (default). 0 1 data written to an input register is not copied to a dac register. the dac output is not updated. 1 0 data in the input registers is copied to the corresponding dac registers. when the data has been transferred, the dac outputs are updated simultaneously. 1 1 reserved. dac readback the input register of each dac can be read back via the i 2 c i nterface. this can be useful to confirm that the data was received correctly before writing to the ldac register or simply checking what value was last loaded to a dac. data can be read back from a dac only when no adc conversion sequence is taking place. a dac input register can be read back using the sequence s hown in figure 32 or figure 33 . the mode bits , bits[d3:d0] , of the pointer register, 0b0101 , select which dac input register is to be read back. when the dac register is read back , the msb of the most significant data byte is a 1 to indicate that the result is an adc register. the next three bits (bi ts[ d14:d12]) contain the dac register address (see table 15) and bits[d11:d0] contain the dac r egister value. figure 36 shows an example of reading the input register of dac2. table 14 . dac pointer byte address dac address d 7 d 6 d 5 d 4 d3 d2 d1 d0 dac0 0 0 0 1 0 0 0 0 dac1 0 0 0 1 0 0 0 1 dac2 0 0 0 1 0 0 1 0 dac3 0 0 0 1 0 0 1 1 dac4 0 0 0 1 0 1 0 0 dac5 0 0 0 1 0 1 0 1 dac6 0 0 0 1 0 1 1 0 dac7 0 0 0 1 0 1 1 1 table 15 . dac data register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 dac a ddress 12 - bit dac data figure 36 . dac input register readback s = start condition p = stop condition a = acknowledge rs = repeat start a p s a a 0b01010010 0b1010xxx 0bxxxxxxx rs a pointer byte dacaddress and 4 msbs dac lsbs slave address + w a slave address + r 12507-018
ad5593r data sheet rev. 0 | page 24 of 28 adc operation the adc channels of the ad5593r operate as a traditional multichannel adc, where each serial transfer selects the next channel for conversion. the user must write to the adc sequence register (see table 17 ) to select the input channels to be included in the conversion sequence before initiating any conversions. this is done using the i 2 c write sequence shown in figure 31 . when writing to the adc sequence register, select which channels are to be convert ed in sequence. the user can also set the rep bit to have the adc repeat conversions i n the sequence. when the sequence register has been written to, the adc beg ins to track the first channel in the sequence. adc data can be read from the ad5593r using any of the three read operations shown in figure 32, figure 33 , and figure 34 , with the i 2 c block read ( figure 34) being the most efficient. if more than one channel is selected in the adc sequence register, the adc converts all selected channels sequentially in ascending order. conversion is started by the rising edge of scl at the acknowledge ( ack ) preceding the msb (see figure 34 ). i f the rep bit is set after all of the selected channels in the sequence register have been converted, the adc repeats the sequence. if the rep bit is clear, the adc clocks out the last result on subsequent i 2 c reads. figure 37 shows how to configure the ad5593r to perform adc conversions. in step 1, i/o7 and i/o0 are configured as adcs. step 2 writes to the adc configuration register, sets the rep bit, and selects adc7 and adc0 for inclusion in the conversion sequence. step 3 selects the adcs for reading and step 4 begins reading the adc results. the conversions are repeated until a stop condition is given by the controller. the adc sequence can be changed by writing the new sequence to the adc sequence register when conversions are not taking place. when a new sequence is written, any channels remaining to be converted from the earlier sequence are ignored and the adc starts converting the first channel of the new sequence. to stop t he adc conversion sequence , clear t h e r e p, t e m p, and adc7 to adc0 bits in the adc sequence r egister to 0. table 16 . adc sequence register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved rep temp adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 table 17 . adc sequence register descriptions bits description d15 to d10 reserved; set this bit to 0 d9 rep: adc sequence repeat 0 = sequence repetition disabled (default) 1 = sequence repetition enabled d8 temp: i nclude temperature indicator in adc sequence 0 = disable temperature indicator readback (default) 1 = enable temperature indicator readback d7 to d0 setting these bits to 1 includes the appropriate adc in the conversion sequence; by default no channels are included figure 37 . configuring the adc for conversion 12507-019 s = start condition p = stop condition a = acknowledge p a p s a a 0b00000100 0b00000000 0b10000001 a pointer byte most significant data byte least significant data byte slave address + w step1 a s a a 0b01000000 adc7 result (msb) adc7 result (lsb) a slave address + r step4 a p s a a 0b00000010 0b00000010 0b10000001 a slave address + w step2 p s a 0b01000000 a slave address + w step3 a a adc7 result (msb) adc7 result (lsb) a a adc0 result (msb) adc0 result (lsb) a a adc0 result (msb) adc0 result (lsb)
data sheet ad5593r rev. 0 | page 25 of 28 gpio operation each of the i/o x pins of the ad5593r can be configured to operate as a general - purpose, digital input or output pin. the function of the pins is determined by writing to the appropriate bit in the gpio read configuration and gpio write configuration registers using the 4 - byte i 2 c write shown in figure 31. setting pins as outputs to set a pin as a general - purpose output, set the appropriate bit in the gpio write configuration register to 1. for example, s etting bit d0 to 1 enables i/o0 as a general - purpose output. the outputs can be independently configured as push/pull or open - drain outputs. when in push/pull configuration, the output is driven to v dd or gnd as determined by the data in the gpio write da ta register. when in open - drain configuration, the output is driven to gnd when a data bit in the gpio write data register sets the pin low. when the pin is set high, the output is not driven and must be pulled high by an external resistor. this allows mul tiple output pins to be tied together. if all the pins are normally high, it allows one pin to pull down the others. this is commonly used where multiple pins are used to trigger an alarm or interrupt pin. the state of the output pin is controlled by setti ng or clearing the bits in the gpio write data register (pointer byte = 0b00001001). a data bit is ignored if it is written to a location that is not configured as an output. table 18 . gpio write configuration register descriptions bits description d15 to d8 reserved; set these bits to 0 d7 to d0 select pins as gpio outputs d [7:0] = 1: i/o [7:0] is a general - purpose output pin d [7:0] = 0: i/o [7:0] function is determined by the pin configuration registers (default) table 19 . gpio open - drain control register descriptions bits description d15 to d8 reserved; set these bits to 0 d7 to d0 sets output pins as open - drain d [7:0] = 1: i/o [7:0] is an open - drain output pin d [7:0] = 0: i/o [7:0] is a push/pull output pin (default) table 20 . gpio write data register descriptions bits description d15 to d8 reserved; set these bits to 0 d7 to d0 sets the state of a gpio output d[7:0] = 1: i/o[7:0] is a logic 1 d [7:0] = 0: i/o [7:0] is a l ogic 0 (default) setting pins as inputs to s e t an i/o x pin as a general - purpose input, set the appropriate bit in the gpio read configuration register to 1. for example, setting bit d0 to 1 enables i/o0 as a general - purpose input. to read the state of general - purpose inputs, set the pointer byte to 0b0110 0 000 (see table 8 ) using any of the read operations shown in figure 32, figure 33 , and figure 34 . the status of any i/o pin set as a general - purpose input appears in the appropriate bit location in the least significant data byte. three - state pins the i/o x pins can be set to three - state by writing to the three - state configuration register (pointer byte = 0b00001101) as shown in table 21. table 21 . three - state configuration register descriptions bits description d15 to d8 reserved; set these bits to 0 d7 to d0 set pins as three - state outputs d [7:0] = 1: i/o [7:0] is a three - state output pin d [7:0] = 0: i/o [7:0] function is determined by the pin configuration registers (default) 85 k? pull - down pins the i/o x pins can be connected to gnd via a pull - down resistor (8 5 k?) by setting the appropriate bits in the pull - down configura tion register (pointer byte = 00000110) as shown in table 22. table 22 . pull - down configuration register descriptions bits description d15 to d8 reserved; set these bits to 0 d7 to d0 set pins as weak pull - down outputs d [7:0] = 1: i/o [7:0 is connected to gnd via an 85 k ? pull - down resistor d [7:0] = 0: i/o [7:0] function is determined by the pin configuration registers (default)
ad5593r data sheet rev. 0 | page 26 of 28 power - down/reference contr ol the ad5593r ha s a power - down/reference control register (pointer byte = 0b00001011) that reduce s the power consumption when certain functions are not needed. the pow er - down register allows any channels set as dacs to be placed in a power - down state individually. when in power - down, the dac outputs are three - stated. when a dac channel is returned into normal mode, the dac output returns to its previous value. the inter nal reference and its buffer are powered down by default and are enabled by setting the en_ref bit in the power - down register. the internal reference voltage then appears at the v ref pin. there is no dedicated power - down function for the adc, but the adc is automatically powered down if none of the i/o x pins are selected as adcs. the adc powers up if a read of the temperature indicator is initiated. the pd_all bit powers down all the dacs, the reference, its buffer , and the adc . the pd_all bit also overrid es the settings of bit d9 to bit d0. table 23 shows the power - down register. reset function the ad5593r can be reset to its default conditions by writing 0x0dac to the reset register (pointer byte = 0b00001111). this resets all registers to their default values and reconfigures the i/o x pins to their default values (85 k? pull - down to gnd). the reset functi on takes 100 s maximum and new data must not be written to the ad5593r during this time. the ad5593r has a reset pin that performs the same function. for normal operation, reset is tied high. a falling edge on reset triggers the reset function. table 23. power - down register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 1 pd_all en_ref 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 table 24 . ldac mode register descriptions bits bit name description d10 pd_all 0 = the power - down states of the reference and dacs are determined by d9 and d7 to d0 (default). 1 = the reference, the dacs, and the adc are powered down. d9 en_ref 0 = the reference and its buffer are powered down (default). set t his bit if an external reference is used. 1 = the reference and its buffer are powered up. the reference is available on the v ref pin. d7 to d0 pd7 to pd0 0 = the channel is in normal operating mode (default). 1 = the channel is powered down if it is configured as a dac.
data sheet ad5593r rev. 0 | page 27 of 28 applications information microprocessor interfacing microprocessor interfacing to the ad5593r is via a serial bus using a standard i 2 c protocol. the communications channel requires a 2-wire interface consisting of a clock signal and a data signal. ad5593r to adsp-bf537 interface the i 2 c interface of the ad5593r is designed to be easily connected to industry-standard dsps and microcontrollers. figure 38 shows the ad5593r connected to the analog devices blackfin? dsp. the blackfin has an integrated i 2 c port that can be connected directly to the i 2 c pins of the ad5593r . figure 38. adsp-bf537 interface layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board (pcb) on which the ad5593r is mounted must be designed so that the ad5593r lies on the analog plane. the ad5593r must have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor must have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. adsp-bf537 scl scl sda sda reset pf8 ad55593r 12507-164
ad5593r data sheet rev. 0 | page 28 of 28 outline dimensions figure 39 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad5593rbruz ?40c to +105c 16 - lead tssop ru -16 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab ? 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12507 -0- 8/14(0)

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